A COF (Chip On Film) in which a semiconductor chip made up of LSI and other components is mounted on a film substrate is used as a package for liquid crystal driver. In case of the COF, bump electrodes are provided at a predetermined alignment pitch in a periphery of the semiconductor chip. These bump electrodes are bonded with the inner leads to connect between the semiconductor chip and the film substrate. That is, as shown in FIG. 9(a), bump electrodes 18 are provided on a semiconductor chip 16, and the bump electrodes 18 are connected respectively to inner leads 10 supported by a film substrate (not shown). The inner lead 10, as shown in FIG. 9(b), is placed linearly from the edge, which is the end of the semiconductor chip 16, to the bump electrode 18 and is bonded with the bump electrode 18.
In recent years, with the development of micro-fabrication, multi-outputs has been advanced by increase in the number of bump electrodes for the purpose of connecting input and output terminals of the semiconductor chip 16 to external wires. Moreover, size reduction of the semiconductor chip 16 has been advanced in terms of size reduction of a semiconductor device and other reasons. For the realization of the multi-outputs and size reduction of the semiconductor chip 16, improvement in fine pitch of the bump electrodes 18 on the semiconductor chip 16 must be advanced.
Specifically, as shown in FIG. 10(a), bump electrodes 19 aligned in a periphery of the semiconductor chip 16 are arranged at high density, allowing for improvement in fine pitch of the bump electrodes. Thus, a high-density arrangement of the bump electrodes 19, as shown in FIG. 10(b), needs a smaller distance between the bump electrodes 19 or reduction in width of the bump electrode 19.
However, reduction in distance between the bump electrodes 19 or reduction in width of the bump electrode 19 causes a problem of lowering a bonding accuracy in bonding between the bump electrode 19 and an inner lead 11. That is, the bump electrode 19 on the semiconductor chip 16 is bonded with the inner lead 11 on a film substrate by thermocompression bonding. This bonding causes the thermal expansion of the film substrate made up of organic material at a part subjected to thermocompression bonding, resulting in approximately 10 μm to 20 μm stretch of the film substrate. This stretch of the film substrate causes variations in the positions of the inner leads 11 on the film substrate. Therefore, the inner lead 11 provided on the film substrate so as to correspond to the position where the bump electrode 19 is provided on the semiconductor chip 16 may be shifted from the position where the bump electrode 19 is provided.
When the semiconductor chip 16 is a rectangle, shifted positions between the inner lead 11 and the bump electrode 19 on the semiconductor chip 16 caused by the thermal expansion in thermocompression bonding occurs especially at the bump electrodes 19 provided along the end part on a long side of the semiconductor chip 16, not at the bump electrodes 19 in a central part of the semiconductor chip 16. This is because the thermal expansion of the film substrate cumulatively increases with increasing distance to the end part of the semiconductor chip 16.
The above shifted position of the inner lead 11 causes lowering in bonding accuracy in bonding between the bump electrode 19 and the inner lead 11. That is, in thermocopression bonding, due to the shifted position of the inner lead 11, the inner lead 11 comes into contact with a bump electrode which is not an intended bump electrode 19 to be bonded with, resulting in shorts and lead defects.
For these reasons, there is a limit of reduction in distance between the bump electrodes 19 or reduction in width of the bump electrode 19, and therefore, there is a limit of improvement in fine pitch of the inner leads 11. Specifically, in the currently mass-produced COF shown in FIG. 10(a), as shown in FIG. 10(b), a width w10 of the bump electrode 19 is 25 μm, and a distance d10 between the bump electrodes 19 is 15 μm. From this, an alignment pitch m10 of the bump electrode 19 becomes 40 μm. That is, at the current bonding accuracy, a pitch p10 of the inner leads in the COF is as large as approximately 40 μm. Thus, in the COF shown in FIG. 10(a), reduction in distance between the bump electrodes 19 or reduction in width of the bump electrode 19 might cause shorts and leak defects, which results in the difficulty of further improvement in fine pitch.
As a technique for improving fine pitch, as shown in FIG. 11(a), suggested is a technique of arranging bump electrodes 17a and 17b in a staggered manner in a periphery of the semiconductor chip 16 (For example, Japanese Laid-Open Patent Application No. 335692/1995 (Tokukaihei 7-335692; published on Dec. 22, 1995), Japanese Laid-Open Patent Application No. 269611/2000 (Tokukai 2000-269611; published on Sep. 29, 2000), etc.). In this case, when the bump electrodes 17a and 17b are arranged in a staggered manner, a bump electrode 17a located on the outer side (hereinafter referred to as outer-side bump electrode) is bonded with an inner lead 12a arranged linearly extending from the edge of the semiconductor chip 16, as described with reference to FIG. 9(a) and FIG. 9(b). Further, to a bump electrode 17b located on the inner side (hereinafter referred to as inner-side bump electrode), arranged is one inner lead 12b through the passage between the outer-side bump electrodes 17a, extending from the edge of the semiconductor chip 16.
In such an arrangement, as shown in FIG. 11(b), the outer-side bump electrodes 17a are spaced at a predetermined distance so that the inner lead 12b bonded with the inner-side bump electrode 17b does not come into contact with the outer-side bump electrode 17a. Moreover, the inner-side bump electrode 17b is so arranged as to be linearly bonded with the inner lead 12b passing through the passage between the outer-side bump electrodes 17a. 
Thus, the outer-side bump electrodes 17a are spaced at a predetermined distance to arrange the inner lead 12b, so that an alignment pitch of the outer-side bump electrodes 17a is smaller than the alignment pitch of the bump electrodes 19 of the COF shown in FIG. 10(a). On the other hand, in the COF shown in FIG. 11(a), the bump electrodes 17a and 17b are arranged in a staggered manner, so that the bump electrodes 17a and 17b can be arranged at high density on the semiconductor chip 16 as in the case of the COF shown in FIG. 10(a).
However, there is a problem that a pitch of the inner leads in the conventional COF of bump electrodes arranged in a staggered manner is as large as approximately 35 μm.
That is, as shown in FIG. 11(b), when the inner leads 12a and 12b each having a width v11 of 15 μm are bonded respectively with the bump electrodes 17a and 17b each having a width w11 of 25 μm so as to pass the center of the bump electrodes 17a and 17b, and a distance f11 between the outer-side bump electrode 17a and the inner lead 12b arranged between the outer-side bump electrodes 17a is 15 μm, a pitch p11 of the inner leads becomes 35 μm.
For further improvement in fine pitch, a width of the bump electrode 17a should be reduced. However, reduction in width of the bump electrode 17a lowers an accuracy of thermocompression bonding between the semiconductor chip 16 and the inner leads 12a and 12b, which tends to occur shifted positions of the inner leads 12a and 12b. As described above, the shifted position of the inner lead 12b causes shorts and leak defects. Moreover, reduction in width of the bump electrodes 17a and 17b in the COF shown in FIG. 11(b) requires enhancement of bonding accuracy of the inner leads 12a and 12b. Therefore, at the current bonding accuracy, further improvement in fine pitch of the inner leads is difficult to realize.
Thus, the conventional COF has a problem that there is a limit of improvement in fine pitch and 35 μm or less inner lead pitch is difficult to attain. Impossibility of realization of improvement in fine pitch of the inner leads results in impossibility of size reduction of the semiconductor chip. Further, this reduces yields of a semiconductor chip inside a wafer, resulting in the difficulty in reduction of costs.